38 search results - page 3 / 8 » Evaluating Fault Emulation on FPGA |
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
DFT
2002
IEEE
13 years 11 months ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
FPL
2001
Springer
13 years 10 months ago
2001
Springer
Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its eff...
ET
2007
13 years 6 months ago
2007
This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a...
CCECE
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper describes a model and a setup for emulating fractal and multifractal noise for the measurement and evaluation of performance of ZigBee mesh networks intended for harsh ...