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» Evaluating Fault Emulation on FPGA
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GLVLSI
2009
IEEE
323views VLSI» more  GLVLSI 2009»
13 years 4 months ago
MYGEN: automata-based on-line test generator for assertion-based verification
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...
FGCN
2007
IEEE
109views Communications» more  FGCN 2007»
14 years 21 days ago
Flow Balancing Hardware for Parallel TCP Streams on Long Fat Pipe Network
Parallel TCP streams are used for data transfer between clusters in today's high performance applications. When parallel TCP streams are used on LFN, part of streams fail to ...
Yutaka Sugawara, Mary Inaba, Kei Hiraki
IOLTS
2005
IEEE
125views Hardware» more  IOLTS 2005»
13 years 12 months ago
Design of a Self Checking Reed Solomon Encoder
— In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in G...
Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco...
OSN
2011
12 years 9 months ago
A parallel iterative scheduler for asynchronous Optical Packet Switching networks
—This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. O...
Pablo Pavón-Mariño, M. Victoria Buen...
CODES
2008
IEEE
14 years 25 days ago
Symbolic voter placement for dependability-aware system synthesis
This paper presents a system synthesis approach for dependable embedded systems. The proposed approach significantly extends previous work by automatically inserting fault detect...
Felix Reimann, Michael Glabeta, Martin Lukasiewycz...