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» Evaluating Hardware Compilation Techniques
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DATE
2002
IEEE
63views Hardware» more  DATE 2002»
15 years 2 months ago
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs
Ashok Halambi, Aviral Shrivastava, Partha Biswas, ...
ASPDAC
2010
ACM
251views Hardware» more  ASPDAC 2010»
14 years 7 months ago
A new compilation technique for SIMD code generation across basic block boundaries
Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji...
CC
2008
Springer
240views System Software» more  CC 2008»
14 years 11 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
90
Voted
HPCA
1997
IEEE
15 years 1 months ago
Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results
This paper introduces a new architectural approach that supports compiler-synthesized dynamic branch predication. In compiler-synthesized dynamic branch prediction, the compiler g...
David I. August, Daniel A. Connors, John C. Gyllen...
EUROMICRO
1998
IEEE
15 years 1 months ago
Hardware to Software Migration with Real-Time Thread Integration
This paper introduces thread integration, a new method of providing low-cost concurrency for microcontrollers and microprocessors. This post-pass compiler technology effectively i...
Alexander G. Dean, John Paul Shen