201 search results - page 18 / 41 » Evaluating Run-Time Techniques for Leakage Power Reduction |
143
Voted
ICCAD
2003
IEEE
15 years 10 months ago
2003
IEEE
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
121
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DAC
1999
ACM
15 years 6 months ago
1999
ACM
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
115
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ISCAS
2007
IEEE
15 years 8 months ago
2007
IEEE
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
162
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RTSS
1998
IEEE
15 years 6 months ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
FCCM
2008
IEEE
15 years 8 months ago
2008
IEEE
Power reduction is becoming more important as circuit size increases. This paper presents a tool called PowerCutter which employs accuracy-guaranteed word-length optimization to r...