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» Evaluating Statistical Power Optimization
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MICRO
2002
IEEE
171views Hardware» more  MICRO 2002»
15 years 2 months ago
Orion: a power-performance simulator for interconnection networks
With the prevalence of server blades and systems-ona-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limite...
Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad...
ICML
2008
IEEE
15 years 10 months ago
Multi-classification by categorical features via clustering
We derive a generalization bound for multiclassification schemes based on grid clustering in categorical parameter product spaces. Grid clustering partitions the parameter space i...
Yevgeny Seldin, Naftali Tishby
ICCD
2006
IEEE
118views Hardware» more  ICCD 2006»
15 years 7 months ago
A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...
Jinwen Xi, Peixin Zhong
ICC
2009
IEEE
144views Communications» more  ICC 2009»
14 years 7 months ago
Green DSL: Energy-Efficient DSM
Dynamic spectrum management (DSM) has been recognized as a key technology for tackling multi-user crosstalk interference for DSL broadband access. Up to now, DSM design has mainly ...
Paschalis Tsiaflakis, Yung Yi, Mung Chiang, Marc M...
JTRES
2010
ACM
14 years 10 months ago
Cyclic executive for safety-critical Java on chip-multiprocessors
Chip-multiprocessors offer increased processing power at a low cost. However, in order to use them for real-time systems, tasks have to be scheduled efficiently and predictably. I...
Anders P. Ravn, Martin Schoeberl