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MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
15 years 5 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
SASP
2008
IEEE
183views Hardware» more  SASP 2008»
15 years 6 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
JCM
2007
115views more  JCM 2007»
14 years 11 months ago
eEPC: an EPCglobal-compliant Embedded Architecture for RFID-based Solutions
— Radio Frequency Identification (RFID) technology has a lot of potential to improve visibility across the supply chain and automate the business processes. This paper describes ...
Franco Fummi, Giovanni Perbellini
LWA
2008
15 years 1 months ago
Labeling Clusters - Tagging Resources
In order to support the navigation in huge document collections efficiently, tagged hierarchical structures can be used. Often, multiple tags are used to describe resources. For u...
Korinna Bade, Andreas Nürnberger
HICSS
2003
IEEE
124views Biometrics» more  HICSS 2003»
15 years 5 months ago
Knowledge Map Creation and Maintenance for Virtual Communities of Practice
This paper proposes a knowledge map management system to facilitate knowledge management in virtual communities of practice. To realize the proposed knowledge map management, we d...
Fu-ren Lin, Chih-ming Hsueh