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VEE
2010
ACM
327views Virtualization» more  VEE 2010»
15 years 4 months ago
AASH: an asymmetry-aware scheduler for hypervisors
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
Vahid Kazempour, Ali Kamali, Alexandra Fedorova
SC
2009
ACM
15 years 4 months ago
Allocator implementations for network-on-chip routers
The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we...
Daniel U. Becker, William J. Dally
VEE
2009
ACM
146views Virtualization» more  VEE 2009»
15 years 4 months ago
Achieving 10 Gb/s using safe and transparent network interface virtualization
: © Achieving 10 Gb/s using Safe and Transparent Network Interface Virtualization Kaushik Kumar Ram, Jose Renato Santos, Yoshio Turner, Alan L. Cox, Scott Rixner HP Laboratories H...
Kaushik Kumar Ram, Jose Renato Santos, Yoshio Turn...
IEEECIT
2009
IEEE
15 years 4 months ago
A Highly Efficient Inter-domain Communication Channel
—With virtual machine technology, distributed services deployed in multiple cooperative virtual machines, such as multi-tier web services, may reside on one physical machine. Thi...
Hongyong Zang, Kuiyan Gu, Yaqiong Li, Yuzhong Sun,...
ICCD
2004
IEEE
98views Hardware» more  ICCD 2004»
15 years 6 months ago
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharide...