Sciweavers

417 search results - page 34 / 84
» Evaluating kilo-instruction multiprocessors
Sort
View
PARLE
1994
15 years 2 months ago
Using Reference Counters in Update-Based Coherent Memory
Abstract. As the disparity between processor and memory speed continues to widen, the exploitation of locality of reference in shared-memory multiprocessors becomes an increasingly...
Evangelos P. Markatos, Catherine E. Chronaki
SIGMETRICS
1990
ACM
129views Hardware» more  SIGMETRICS 1990»
15 years 2 months ago
An Analytical Model of Multistage Interconnection Networks
Multiprocessors require an interconnection network to connect processors with memory modules. The performance of the interconnection network can have a large effect upon overall s...
Darryl L. Willick, Derek L. Eager
DATE
2004
IEEE
159views Hardware» more  DATE 2004»
15 years 2 months ago
Compositional Memory Systems for Data Intensive Applications
To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set ba...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
EUROPAR
2006
Springer
15 years 2 months ago
Tying Memory Management to Parallel Programming Models
Stand-alone threading libraries lack sophisticated memory management techniques. In this paper, we present a methodology that allows threading libraries that implement non-preempti...
Ioannis E. Venetis, Theodore S. Papatheodorou
DATE
2005
IEEE
111views Hardware» more  DATE 2005»
15 years 19 days ago
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan