65 search results - page 9 / 13 » Evaluating register file size in ASIP design |
78
Voted
VLSID
2004
IEEE
15 years 9 months ago
2004
IEEE
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
62
Voted
SIGMETRICS
1990
ACM
15 years 1 months ago
1990
ACM
Recently we presented several disk array architectures designed to increase the data rate and I/O rate of supercomputing applications, transaction processing, and file systems [Pat...
APPT
2003
Springer
15 years 2 months ago
2003
Springer
The speed of storing and fetching data on SCSI disks has a great restriction on the efficiency of SAN based on Fiber Channel Network. In this paper, a high-efficient FC-SAN storage...
113
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EUROPAR
2010
Springer
14 years 10 months ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
70
Voted
SIGMETRICS
2006
ACM
15 years 3 months ago
2006
ACM
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance scheme...