207 search results - page 22 / 42 » Evaluating the Performance of Software Cache Coherence |
113
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SIGARCH
2008
15 years 11 days ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
DAC
2004
ACM
16 years 1 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
110
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SPAA
2006
ACM
15 years 6 months ago
2006
ACM
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
103
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SAC
2004
ACM
15 years 5 months ago
2004
ACM
Web cache replacement algorithms have received a lot of attention during the past years. Though none of the proposed algorithms deals efficiently with all the particularities of t...
131
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CASES
2007
ACM
15 years 4 months ago
2007
ACM
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...