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» Evaluating the Performance of Software Cache Coherence
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ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 1 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
SIGIR
2010
ACM
15 years 1 months ago
Evaluating whole-page relevance
Whole page relevance defines how well the surface-level representation of all elements on a search result page and the corresponding holistic attributes of the presentation respon...
Peter Bailey, Nick Craswell, Ryen W. White, Liwei ...
CODES
2008
IEEE
15 years 4 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
15 years 4 months ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
ISPASS
2005
IEEE
15 years 3 months ago
Reaping the Benefit of Temporal Silence to Improve Communication Performance
Communication misses--those serviced by dirty data in remote caches--are a pressing performance limiter in shared-memory multiprocessors. Recent research has indicated that tempor...
Kevin M. Lepak, Mikko H. Lipasti