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» Evaluating the Performance of Software Cache Coherence
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ASPLOS
2012
ACM
13 years 5 months ago
Scalable address spaces using RCU balanced trees
Software developers commonly exploit multicore processors by building multithreaded software in which all threads of an application share a single address space. This shared addre...
Austin T. Clements, M. Frans Kaashoek, Nickolai Ze...
HPCA
2011
IEEE
14 years 1 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...
EUROMICRO
2002
IEEE
15 years 2 months ago
Feasibility Analysis for Web Project Engineering Encoded as Rule-Based Expert System
The initial steps in carrying out a feasibility analysis for a web project, based on information obtained interactively from a prospective client, are modelled as a rulebased expe...
Pablo Gervás, Juan José Escribano Ot...
CODES
2009
IEEE
15 years 2 months ago
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators
Reconfigurable Processors utilize a reconfigurable fabric (to implement application-specific accelerators) and may perform runtime reconfigurations to exchange the set of deployed...
Lars Bauer, Muhammad Shafique, Jörg Henkel
MICRO
1995
IEEE
102views Hardware» more  MICRO 1995»
15 years 1 months ago
Zero-cycle loads: microarchitecture support for reducing load latency
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
Todd M. Austin, Gurindar S. Sohi