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» Evaluating the performance engineering process
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107
Voted
VLSID
2005
IEEE
121views VLSI» more  VLSID 2005»
16 years 5 months ago
Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications
In this paper, we have studied and compared the RF performance metrics, unity gain frequency (ft) and Noise Figure (NF), of the devices with channel engineering consisting of halo...
R. Srinivasan, Navakanta Bhat
143
Voted
CODES
2001
IEEE
15 years 8 months ago
Evaluating register file size in ASIP design
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, P...
TGC
2005
Springer
15 years 10 months ago
Engineering Runtime Requirements-Monitoring Systems Using MDA Technologies
The Model-Driven Architecture (MDA) technology toolset includes a language for describing the structure of meta-data, the MOF, and a language for describing consistency properties ...
James Skene, Wolfgang Emmerich
CCECE
2006
IEEE
15 years 11 months ago
Single-Sensor Image Compression from the End-User's Perspective
Single-sensor imaging pipelines comprised of various image compression and demosaicking solutions are presented. Since the end-user usually inspects captured images available in t...
Rastislav Lukac, Konstantinos N. Plataniotis
AHS
2006
IEEE
137views Hardware» more  AHS 2006»
15 years 11 months ago
Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
Wing On Fung, Tughrul Arslan, Sami Khawam