668 search results - page 104 / 134 » Evaluation of Parallel Logic Simulation Using DVSIM |
132
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IPPS
2006
IEEE
15 years 9 months ago
2006
IEEE
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
121
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IPPS
2006
IEEE
15 years 9 months ago
2006
IEEE
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
140
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MICRO
2009
IEEE
15 years 9 months ago
2009
IEEE
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
153
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ICDCS
2011
IEEE
14 years 2 months ago
2011
IEEE
—The number of real-world applications that require QoS guarantees is constantly increasing and they often follow the publish/subscribe (pub/sub) messaging paradigm, which provid...
126
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ISLPED
2004
ACM
15 years 8 months ago
2004
ACM
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...