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» Evaluation of Parallel Logic Simulation Using DVSIM
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HPCA
2006
IEEE
15 years 12 months ago
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors
Simulation is an important means of evaluating new microarchitectures. Current trends toward chip multiprocessors (CMPs) try the ability of designers to develop efficient simulato...
David A. Penry, Daniel Fay, David Hodgdon, Ryan We...
106
Voted
DAC
2010
ACM
15 years 2 months ago
Efficient fault simulation on many-core processors
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...
Michael A. Kochte, Marcel Schaal, Hans-Joachim Wun...
95
Voted
IPPS
1994
IEEE
15 years 3 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
EUROPAR
2007
Springer
15 years 5 months ago
Hirschberg's Algorithm on a GCA and Its Parallel Hardware Implementation
We present in detail a GCA (Global Cellular Automaton) algorithm with 3n cells for Hirschberg’s algorithm which determines the connected components of a n-node undirected graph w...
Johannes Jendrsczok, Rolf Hoffmann, Jörg Kell...
IPPS
1998
IEEE
15 years 3 months ago
Implementing Parallelism in Random Discrete Event-Driven Simulation
Abstract. The inherently sequential nature of random discrete eventdriven simulation has made parallel and distributed processing di cult. This paper presents a method of applying ...
Marc Bumble, Lee D. Coraor