668 search results - page 13 / 134 » Evaluation of Parallel Logic Simulation Using DVSIM |
DAC
2009
ACM
16 years 19 days ago
2009
ACM
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
WSC
1998
15 years 29 days ago
1998
Parallel discrete event simulation (PDES) decreases a simulation's runtime by splitting the simulation's work between multiple processors. Many users avoid PDES because ...
103
Voted
CF
2009
ACM
14 years 9 months ago
2009
ACM
Emulation sits between simulation and experimentation to complete the set of tools available for software designers to evaluate their software and predict behavior under condition...
103
Voted
PPSN
2004
Springer
15 years 5 months ago
2004
Springer
This paper introduces a new evaluation function, called δ, for the Bandwidth Minimization Problem for Graphs (BMPG). Compared with the classical β evaluation function used, our Î...
IPPS
1997
IEEE
15 years 3 months ago
1997
IEEE
This paper analyses alternatives for the parallelization of the Simulated Annealing algorithm when applied to the placement of modules in a VLSI circuit considering the use of PVM...