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» Evaluation of Parallel Logic Simulation Using DVSIM
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ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
15 years 3 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
LCN
2002
IEEE
15 years 4 months ago
Parallel Packet Switching Using Multiplexors with Virtual Input Queues
Parallel Packet Switches (PPS) use internal, parallel switch planes that operate at less than line speed. A PPS can scale-up to faster line speeds than a single-plane switch can. ...
Ahmed Aslam, Kenneth J. Christensen
83
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WSC
2001
15 years 1 months ago
Managing event traces for a web front-end to a parallel simulation
To enhance the widespread use of a parallel supply chain simulator, a web front-end that enables access at any time and from any location has been developed. The front-end provide...
Boon-Ping Gan, Li Liu, Zhengrong Ji, Stephen John ...
SPRINGSIM
2008
15 years 1 months ago
Data parallel execution challenges and runtime performance of agent simulations on GPUs
Programmable graphics processing units (GPUs) have emerged as excellent computational platforms for certain general-purpose applications. The data parallel execution capabilities ...
Kalyan S. Perumalla, Brandon G. Aaby
ISCA
1987
IEEE
65views Hardware» more  ISCA 1987»
15 years 3 months ago
Performance Studies of a Parallel Prolog Architecture
This paper presents a new multiprocessor architecture for the parallel execution of logic programs, developed as part of the Aquarius Project. This architecture is designed to sup...
Barry S. Fagin, Alvin M. Despain