668 search results - page 28 / 134 » Evaluation of Parallel Logic Simulation Using DVSIM |
119
Voted
FCCM
2003
IEEE
15 years 8 months ago
2003
IEEE
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
101
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DATE
2000
IEEE
15 years 7 months ago
2000
IEEE
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
104
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JCIT
2010
14 years 10 months ago
2010
An important and fundamental issue in designing structured peer-to-peer networks is the tradeoff between the number of logical links and the number of hops. We present a flexible ...
149
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APPT
2009
Springer
15 years 6 months ago
2009
Springer
Abstract. This paper presents a simulator for of a decentralized modular grid scheduler named MaGate. MaGate’s design emphasizes scheduler interoperability by providing intellige...
139
Voted
ICPPW
2003
IEEE
15 years 8 months ago
2003
IEEE
Users have been demanding information “anytime, anywhere”. The notion of accessing diverse and autonomous information repositories with different APIs is not accepted. This ha...