668 search results - page 4 / 134 » Evaluation of Parallel Logic Simulation Using DVSIM |
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SBACPAD
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper discusses the implementation of a numerical algorithm for simulating incompressible fluid flows based on the finite difference method and designed for parallel compu...
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CLUSTER
2007
IEEE
15 years 3 months ago
2007
IEEE
— Various mechanisms for fault-tolerance (FT) are used today in order to reduce the impact of failures on application execution. In the case of system failure, standard FT mechan...
EH
2003
IEEE
15 years 2 months ago
2003
IEEE
In this paper, we perform a comparative study of different heuristics used to design combinational logic circuits. The use of local search hybridized with a genetic algorithm and ...
DAC
1999
ACM
15 years 1 months ago
1999
ACM
: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
A
exible test environment is presented that allows for dierent methods of parallelizing discrete event simulation to be evaluated in a uniform environment. The testbed is portabl...