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» Evaluation of Parallel Logic Simulation Using DVSIM
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PARLE
1994
15 years 7 months ago
Using Reference Counters in Update-Based Coherent Memory
Abstract. As the disparity between processor and memory speed continues to widen, the exploitation of locality of reference in shared-memory multiprocessors becomes an increasingly...
Evangelos P. Markatos, Catherine E. Chronaki
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
15 years 8 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
ICS
2005
Tsinghua U.
15 years 8 months ago
Low-power, low-complexity instruction issue using compiler assistance
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S...
ICDE
1991
IEEE
133views Database» more  ICDE 1991»
15 years 6 months ago
Read Optimized File System Designs: A Performance Evaluation
This paper presents a performance comparison of several file system allocation policies. The file systems are designed to provide high bandwidth between disks and main memory by...
Margo I. Seltzer, Michael Stonebraker
ICPADS
2007
IEEE
15 years 9 months ago
Supporting deadline monotonic policy over 802.11 average service time analysis
In this paper, we propose a real time scheduling policy over 802.11 DCF protocol called Deadline Monotonic (DM). We evaluate the performance of this policy for a simple scenario w...
Inès El Korbi, Leïla Azouz Saïdan...