668 search results - page 5 / 134 » Evaluation of Parallel Logic Simulation Using DVSIM |
DATE
1997
IEEE
15 years 1 months ago
1997
IEEE
Behavioral simulation is faster than gate-level logic simulation, however, the simulation speed is too slow for large systems. Simulation specific machines accelerated simulation ...
65
Voted
SAMOS
2007
Springer
15 years 3 months ago
2007
Springer
Abstract— This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have uniqu...
ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
EUROPAR
2005
Springer
15 years 3 months ago
2005
Springer
In this paper we introduce INSEE, an environment to help in the design of interconnection networks for parallel computing systems. It contains two basic modules: a system to genera...
ICLP
1997
Springer
15 years 1 months ago
1997
Springer
We introduce novel, sound, complete, and locally optimal evaluation strategies for functional logic programming languages. Our strategies combine, in a non-trivial way, two landma...