668 search results - page 62 / 134 » Evaluation of Parallel Logic Simulation Using DVSIM |
132
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ASPDAC
2004
ACM
15 years 8 months ago
2004
ACM
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...
118
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SC
1995
ACM
15 years 6 months ago
1995
ACM
As part of a NASA HPCC Grand Challenge project, we are designing and implementing a parallel atmospheric chemical tracer model that will be suitable for use in global simulations....
119
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HPDC
2006
IEEE
15 years 9 months ago
2006
IEEE
Trace-driven simulation is an important technique used in the evaluation of computer architecture innovations. However using it for studying parallel computers and applications is...
110
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IPPS
2003
IEEE
15 years 8 months ago
2003
IEEE
Our recent work on uniprocessor and single-node multiprocessor (SMP) active memory systems uses address remapping techniques in conjunction with extended cache coherence protocols...
119
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ISHPC
2003
Springer
15 years 8 months ago
2003
Springer
We developed a multithreaded parallel implementation of a sequence alignment algorithm that is able to align whole genomes with reliable output and reasonable cost. This paper pres...