668 search results - page 6 / 134 » Evaluation of Parallel Logic Simulation Using DVSIM |
67
Voted
VTS
2000
IEEE
15 years 1 months ago
2000
IEEE
ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of sim...
CHES
2009
Springer
15 years 4 months ago
2009
Springer
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...
ICA3PP
2010
Springer
14 years 8 months ago
2010
Springer
A new user-friendly visual simulation tool; ViSim is presented. ViSim could be useful for researchers, students, teachers in their works, and for the demonstration of various wirel...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
— Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearopti...
IWANN
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low pow...