668 search results - page 70 / 134 » Evaluation of Parallel Logic Simulation Using DVSIM |
127
click to vote
HPCC
2005
Springer
15 years 8 months ago
2005
Springer
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
133
click to vote
ICDCS
2011
IEEE
14 years 2 months ago
2011
IEEE
—Massively parallel scientific applications, running on extreme-scale supercomputers, produce hundreds of terabytes of data per run, driving the need for storage solutions to im...
127
Voted
HPCA
1999
IEEE
15 years 7 months ago
1999
IEEE
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under p...
124
click to vote
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
117
click to vote
EUROPAR
2009
Springer
15 years 9 months ago
2009
Springer
Abstract In this paper, we focus on the problem of scheduling batches of identical task graphs on a heterogeneous platform, when the task graph consists in a tree. We rely on stead...