668 search results - page 96 / 134 » Evaluation of Parallel Logic Simulation Using DVSIM |
118
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MOBISYS
2003
ACM
16 years 2 months ago
2003
ACM
In this paper, we present a middleware architecture for coordination services in sensor networks that facilitates interaction between groups of sensors which monitor different env...
121
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ICPP
2008
IEEE
15 years 9 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
120
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WSC
2004
15 years 4 months ago
2004
The Virtual Test Bed (VTB) is a prototype of a virtual engineering environment to study operations of current and future space vehicles, spaceports, and ranges. The HighLevel Arch...
101
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ICS
1999
Tsinghua U.
15 years 7 months ago
1999
Tsinghua U.
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
124
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DSD
2002
IEEE
15 years 8 months ago
2002
IEEE
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...