668 search results - page 97 / 134 » Evaluation of Parallel Logic Simulation Using DVSIM |
221
click to vote
Publication
In this paper, we propose a task scheduling algorithm for a multicore processor system which reduces the recovery time in case of a single fail-stop failure of a multicore processo...
239
click to vote
Presentation
In this paper, we propose a task scheduling al-gorithm for a multicore processor system which reduces the recovery time in case of a single fail-stop failure of a multicore process...
126
click to vote
MIDDLEWARE
2004
Springer
15 years 8 months ago
2004
Springer
This paper explores integrating self-tuning updates and sequential consistency to enable transparent replication of large-scale information dissemination services. We focus our at...
139
click to vote
ICDCS
2008
IEEE
15 years 9 months ago
2008
IEEE
The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit the sequentia...
144
click to vote
MICRO
2003
IEEE
15 years 8 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...