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ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
15 years 3 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
64
Voted
PERVASIVE
2005
Springer
15 years 2 months ago
Collaborative Sensing in a Retail Store Using Synchronous Distributed Jam Signalling
The retail store environment is a challenging application area for Pervasive Computing technologies. It has demanding base conditions due to the number and complexity of the interd...
Albert Krohn, Tobias Zimmer, Michael Beigl, Christ...
88
Voted
DOLAP
2004
ACM
15 years 2 months ago
Experimental evidence on partitioning in parallel data warehouses
Parallelism can be used for major performance improvement in large Data warehouses (DW) with performance and scalability challenges. A simple low-cost shared-nothing architecture ...
Pedro Furtado
INFOCOM
2003
IEEE
15 years 2 months ago
User-Level Performance of Channel-Aware Scheduling Algorithms in Wireless Data Networks
— Channel-aware scheduling strategies, such as the Proportional Fair algorithm for the CDMA 1xEV-DO system, provide an effective mechanism for improving throughput performance in...
Sem C. Borst
97
Voted
HPDC
2002
IEEE
15 years 2 months ago
Decoupling Computation and Data Scheduling in Distributed Data-Intensive Applications
In high energy physics, bioinformatics, and other disciplines, we encounter applications involving numerous, loosely coupled jobs that both access and generate large data sets. So...
Kavitha Ranganathan, Ian T. Foster