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DSD
2006
IEEE
110views Hardware» more  DSD 2006»
15 years 5 months ago
A Flexible, Syntax Independent Representation (SIR) for System Level Design Models
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
Ines Viskic, Rainer Dömer
DATE
2006
IEEE
157views Hardware» more  DATE 2006»
15 years 5 months ago
Modeling and simulation of mobile gateways interacting with wireless sensor networks
Sensor networks are emerging wireless technologies; their integration with the existing 2.5G, 3G mobile networks is a key issue to provide advanced services, e.g., health control....
Franco Fummi, Davide Quaglia, Fabio Ricciato, Maur...
FPL
2005
Springer
86views Hardware» more  FPL 2005»
15 years 5 months ago
On the Reliability Evaluation of SRAM-Based FPGA Designs
Benefits of Field Programmable Gate Arrays (FPGAs) have lead to a spectrum of use ranging from consumer products to astronautics. This diversity necessitates the need to evaluate ...
Olivier Héron, Talal Arnaout, Hans-Joachim ...
DATE
2008
IEEE
100views Hardware» more  DATE 2008»
15 years 6 months ago
A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs
When designing heterogeneous MP-SoCs designers have to take into account various objectives such as power, die size, flexibility, performance or programmability. But to be able t...
Bastian Ristau, Torsten Limberg, Gerhard Fettweis
RTAS
2008
IEEE
15 years 6 months ago
Physical Assembly Mapper: A Model-Driven Optimization Tool for QoS-Enabled Component Middleware
This paper provides four contributions to the study of optimization techniques for component-based distributed realtime and embedded (DRE) systems. First, we describe key challeng...
Krishnakumar Balasubramanian, Douglas C. Schmidt