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IPPS
2000
IEEE
15 years 4 months ago
Design and Evaluation of I/O Strategies for Parallel Pipelined STAP Applications
This paper presents experimental results for a parallel pipeline STAP system with I/O task implementation using the parallel file systems on the Intel Paragon and the IBM SP. In ...
Wei-keng Liao, Alok N. Choudhary, Donald Weiner, P...
DAC
2002
ACM
16 years 24 days ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
ICCD
2006
IEEE
118views Hardware» more  ICCD 2006»
15 years 8 months ago
A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...
Jinwen Xi, Peixin Zhong
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
15 years 3 months ago
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
CSIE
2009
IEEE
15 years 27 days ago
On Test Script Technique Oriented Automation of Embedded Software Simulation Testing
Succinct test script with high efficiency is one of key point for automation of embedded software testing. In this paper, we integrated object technique with automated simulation ...
Yongfeng Yin, Bin Liu, Bentao Zheng