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» Evaluation of a High Performance Code Compression Method
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119
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IOLTS
2005
IEEE
125views Hardware» more  IOLTS 2005»
15 years 9 months ago
Design of a Self Checking Reed Solomon Encoder
— In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in G...
Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco...
125
Voted
CVPR
2008
IEEE
15 years 5 months ago
Adaptive region intensity based rigid ultrasound and CT image registration
Rigid registration of intraoperative ultrasound (US) and CT is an important technique to provide real-time guidance for preoperative images and models. Due to the speckle noise an...
Zhijun Zhang
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
15 years 9 months ago
System-level scheduling on instruction cell based reconfigurable systems
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawa...
138
Voted
CORR
2008
Springer
103views Education» more  CORR 2008»
15 years 3 months ago
Generating Random Graphs with Large Girth
We present a simple and efficient algorithm for randomly generating simple graphs without small cycles. These graphs can be used to design high performance Low-Density Parity-Chec...
Mohsen Bayati, Andrea Montanari, Amin Saberi
132
Voted
IEEEPACT
2007
IEEE
15 years 10 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...