Sciweavers

159 search results - page 9 / 32
» Evaluation of an FPGA Implementation of the Discrete Element...
Sort
View
94
Voted
FPL
2008
Springer
207views Hardware» more  FPL 2008»
14 years 11 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana
FPL
2010
Springer
148views Hardware» more  FPL 2010»
14 years 7 months ago
FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators
FPGA devices are mostly utilized for customized application designs with heavily pipelined and aggressively parallel computations. However, little focus is normally given to the FP...
Muhammad Shafiq, Miquel Pericàs, Nacho Nava...
FCCM
2008
IEEE
176views VLSI» more  FCCM 2008»
14 years 9 months ago
The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration
Communications infrastructure for modular reconfiguration of FPGAs needs to support the changing communications interfaces of a sequence of modules. In order to avoid the overhead...
Shannon Koh, Oliver Diessel
AIS
2004
Springer
15 years 1 months ago
Timed I/O Test Sequences for Discrete Event Model Verification
Abstract. Model verification examines the correctness of a model implementation with respect to a model specification. While being described from model specification, implementatio...
Ki Jung Hong, Tag Gon Kim
FPL
2004
Springer
103views Hardware» more  FPL 2004»
15 years 2 months ago
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation ...
Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne L...