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86
Voted
APCSAC
2003
IEEE
15 years 3 months ago
2003
IEEE
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...
EUROPAR
2007
Springer
15 years 3 months ago
2007
Springer
Due to the increasing performance requirements of decoding H.264/AVC in HDTV or larger resolutions, new approaches are necessary to enable real-time processing. According to the cu...
118
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CODES
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
114
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ISCA
1993
IEEE
15 years 3 months ago
1993
IEEE
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
153
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ISCA
2003
IEEE
15 years 5 months ago
2003
IEEE
Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM...