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121
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ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
16 years 13 days ago
Exploring linear structures of critical path delay faults to reduce test efforts
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou
129
Voted
COCO
2007
Springer
89views Algorithms» more  COCO 2007»
15 years 9 months ago
Testing Properties of Constraint-Graphs
We study a model of graph related formulae that we call the Constraint-Graph model. A constraintgraph is a labeled multi-graph (a graph where loops and parallel edges are allowed)...
Shirley Halevy, Oded Lachish, Ilan Newman, Dekel T...
116
Voted
GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
15 years 8 months ago
Mixing ATPG and property checking for testing HW/SW interfaces
A critical part of the design of HW/SW systems concerns the definition of the HW/SW interface. Such interfaces do not directly map a functionality of the system description, but ...
Alessandro Fin, Franco Fummi, Graziano Pravadelli
114
Voted
ISSTA
2006
ACM
15 years 9 months ago
Architecture-based testing using goals and plans
This paper presents a specification-based testing approach that compares software specifications defined at different f abstraction, e.g. architecture and implementation, agai...
Kristina Winbladh, Thomas A. Alspaugh, Hadar Ziv, ...
125
Voted
GECCO
2003
Springer
182views Optimization» more  GECCO 2003»
15 years 8 months ago
Spatial Operators for Evolving Dynamic Bayesian Networks from Spatio-temporal Data
Learning Bayesian networks from data has been studied extensively in the evolutionary algorithm communities [Larranaga96, Wong99]. We have previously explored extending some of the...
Allan Tucker, Xiaohui Liu, David Garway-Heath