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ASPDAC
2004
ACM
112views Hardware» more  ASPDAC 2004»
15 years 9 months ago
Longest path selection for delay test under process variation
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, We...
DFT
2003
IEEE
120views VLSI» more  DFT 2003»
15 years 9 months ago
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS)
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...
Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Che...
135
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ISSRE
2002
IEEE
15 years 8 months ago
Optimal Allocation of Testing Resources for Modular Software Systems
In this paper, based on software reliability growth models with generalized logistic testing-effort function, we study three optimal resource allocation problems in modular softwa...
Chin-Yu Huang, Jung-Hua Lo, Sy-Yen Kuo, Michael R....
VTS
2002
IEEE
109views Hardware» more  VTS 2002»
15 years 8 months ago
Controlling Peak Power During Scan Testing
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...
Ranganathan Sankaralingam, Nur A. Touba
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
15 years 8 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey