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MICRO
1995
IEEE
97views Hardware» more  MICRO 1995»
15 years 8 months ago
Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
Mark Smotherman, Manoj Franklin
EUROPAR
2008
Springer
15 years 6 months ago
Optimized Pipelined Parallel Merge Sort on the Cell BE
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
Jörg Keller, Christoph W. Kessler
SDM
2008
SIAM
118views Data Mining» more  SDM 2008»
15 years 5 months ago
Massive-Scale Kernel Discriminant Analysis: Mining for Quasars
We describe a fast algorithm for kernel discriminant analysis, empirically demonstrating asymptotic speed-up over the previous best approach. We achieve this with a new pattern of...
Ryan Riegel, Alexander Gray, Gordon Richards
NETWORKING
2007
15 years 5 months ago
Interference-Aware Multicasting in Wireless Mesh Networks
Multicasting is one of the most important applications in Wireless Ad hoc Networks and the currently emerging Wireless Mesh Networks. In such networks, interference due to the shar...
Sudheendra Murthy, Abhishek Goswami, Arunabha Sen
174
Voted
CN
2006
107views more  CN 2006»
15 years 4 months ago
BGP session lifetime modeling in congested networks
The reliable Border Gateway Protocol (BGP) is essential for supporting high quality Internet data communication. In present Internet, due to the lack of differentiation mechanism ...
Li Xiao, Guanghui He, Klara Nahrstedt