Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahm...
Abstract. We have presented an optimal algorithm for minimal cost loop problem (MCLP), which consists of finding a set of minimum cost loops rooted at a source node. In the MCLP, t...
The increasing popularity of all-optical networks has led to extensive research on the routing and wavelength assignment problem, also termed as the Routing and Path Coloring probl...
Abstract. We consider variations of two well-known centrality measures, betweenness and closeness, with a different model of information spread. Rather than along shortest paths o...