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CORR
2010
Springer
137views Education» more  CORR 2010»
14 years 12 months ago
Verification of Java Bytecode using Analysis and Transformation of Logic Programs
State of the art analyzers in the Logic Programming (LP) paradigm are nowadays mature and sophisticated. They allow inferring a wide variety of global properties including terminat...
Elvira Albert, Miguel Gómez-Zamalloa, Laure...

Publication
273views
13 years 10 months ago
 Beyond Graphs: A New Synthesis.
Artificial neural networks, electronic circuits, and gene networks are some examples of systems that can be modeled as networks, that is, as collections of interconnected nodes. I...
Mattiussi, Claudio, Dürr, Peter, Marbach, Daniel ...
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
15 years 5 months ago
PipeRoute: a pipelining-aware router for FPGAs
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
Akshay Sharma, Carl Ebeling, Scott Hauck
TABLEAUX
2009
Springer
15 years 6 months ago
A Schemata Calculus for Propositional Logic
We define a notion of formula schema handling arithmetic parameters, indexed propositional variables (e.g. Pi) and iterated conjunctions/disjunctions (e.g. Vn i=1 Pi, where n is a...
Vincent Aravantinos, Ricardo Caferra, Nicolas Pelt...
PLDI
2004
ACM
15 years 5 months ago
Kill-safe synchronization abstractions
e Synchronization Abstractions “Well, it just so happens that your friend here is only mostly dead. There’s a big difference between mostly dead and all dead.” – Miracle Ma...
Matthew Flatt, Robert Bruce Findler