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ISCA
1996
IEEE
124views Hardware» more  ISCA 1996»
15 years 4 months ago
MGS: A Multigrain Shared Memory System
Parallel workstations, each comprising 10-100 processors, promise cost-effective general-purpose multiprocessing. This paper explores the coupling of such small- to medium-scale s...
Donald Yeung, John Kubiatowicz, Anant Agarwal
SPAA
2009
ACM
16 years 11 days ago
NZTM: nonblocking zero-indirection transactional memory
This workshop paper reports work in progress on NZTM, a nonblocking, zero-indirection object-based hybrid transactional memory system. NZTM can execute transactions using best-eff...
Fuad Tabba, Mark Moir, James R. Goodman, Andrew W....
EUROCAST
2007
Springer
131views Hardware» more  EUROCAST 2007»
15 years 3 months ago
Efficient Model Checking of Applications with Input/Output
Most non-trivial applications use some form of input/output (I/O), such as network communication. When model checking such an application, a simple state space exploration scheme i...
Cyrille Artho, Boris Zweimüller, Armin Biere,...
MICRO
1992
IEEE
133views Hardware» more  MICRO 1992»
15 years 3 months ago
Code generation schema for modulo scheduled loops
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
B. Ramakrishna Rau, Michael S. Schlansker, Parthas...
ISCAS
2005
IEEE
146views Hardware» more  ISCAS 2005»
15 years 5 months ago
A novel approach for network on chip emulation
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...