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ASPLOS
2000
ACM
15 years 4 months ago
Evaluating Design Alternatives for Reliable Communication on High-Speed Networks
We systematically evaluate the performance of five implementations of a single, user-level communication interface. Each implementation makes different architectural assumptions ...
Raoul Bhoedjang, Kees Verstoep, Tim Rühl, Hen...
CODES
2006
IEEE
15 years 5 months ago
Integrated analysis of communicating tasks in MPSoCs
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
Simon Schliecker, Matthias Ivers, Rolf Ernst
HPCA
1998
IEEE
15 years 4 months ago
Exploiting Two-Case Delivery for Fast Protected Messaging
We propose and evaluate two complementary techniques to protect and virtualize a tightly-coupled network interface in a multicomputer. The techniques allow efficient, direct appli...
Kenneth Mackenzie, John Kubiatowicz, Matthew Frank...
DATE
2007
IEEE
174views Hardware» more  DATE 2007»
15 years 6 months ago
ATLAS: a chip-multiprocessor with transactional memory support
Chip-multiprocessors are quickly becoming popular in embedded systems. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded appli...
Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy T...
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
14 years 10 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...