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CODES
2003
IEEE
15 years 5 months ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
IPPS
1996
IEEE
15 years 3 months ago
Exploiting the Capabilities of Communications Co-Processors
Communications co-processors (CCPs) have become commonplace in modern MPPs and networks of workstations. These co-processors provide dedicated hardware support for fast communicat...
Klaus E. Schauser, Chris J. Scheiman, J. Mitchell ...
CODES
2003
IEEE
15 years 5 months ago
Security wrappers and power analysis for SoC technologies
Future wireless internet enabled devices will be increasingly powerful supporting many more applications including one of the most crucial, security. Although SoCs offer more resi...
Catherine H. Gebotys, Y. Zhang
SPAA
2012
ACM
13 years 2 months ago
A scalable framework for heterogeneous GPU-based clusters
GPU-based heterogeneous clusters continue to draw attention from vendors and HPC users due to their high energy efficiency and much improved single-node computational performance...
Fengguang Song, Jack Dongarra
SBACPAD
2005
IEEE
112views Hardware» more  SBACPAD 2005»
15 years 5 months ago
Cooperation of Neighboring PEs in Clustered Architectures
Clustered architectures which intend to process data within a localized PE are one of the approaches to increase the performance under the difficulties of the wire delay problems...
Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura