3893 search results - page 112 / 779 » Execution Architectures and Compilation |
ISCA
2002
IEEE
14 years 9 months ago
2002
IEEE
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
SAMOS
2004
Springer
15 years 3 months ago
2004
Springer
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
FPL
2009
Springer
15 years 2 months ago
2009
Springer
Multitasking reconfigurable computers with one or more reconfigurable processors are being used increasingly during the past few years. One of the major challenges in such systems...
PLDI
1995
ACM
15 years 1 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
CAMP
2005
IEEE
15 years 3 months ago
2005
IEEE
Abstract— An image sensor in which each pixel has a processing element is called a vision chip. The vision chip can perform real-time visual processing at a high frame rate of 10...