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GLVLSI
2010
IEEE
141views VLSI» more  GLVLSI 2010»
14 years 10 months ago
Energy-efficient redundant execution for chip multiprocessors
Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chi...
Pramod Subramanyan, Virendra Singh, Kewal K. Saluj...
LOGCOM
2002
85views more  LOGCOM 2002»
14 years 9 months ago
Engineering Executable Agents using Multi-context Systems
In the area of agent-based computing there are many proposals for specific system architectures, and a number of proposals for general approaches to building agents. As yet, howev...
Jordi Sabater, Carles Sierra, Simon Parsons, Nicho...
ICS
2009
Tsinghua U.
15 years 4 months ago
High-performance CUDA kernel execution on FPGAs
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
Alexandros Papakonstantinou, Karthik Gururaj, John...
WCRE
2000
IEEE
15 years 2 months ago
A Reference Architecture for Web Servers
A reference software architecture for a domain defines the fundamental components of the domain and the relations between them. Research has shown the benefits of having a referen...
Ahmed E. Hassan, Richard C. Holt
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
15 years 2 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...