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IAJIT
2010
107views more  IAJIT 2010»
15 years 2 months ago
Low Latency, High Throughput, and Less Complex VLSI Architecture for 2D-DFT
: This paper proposes a pipelined, systolic architecture for two- dimensional discrete Fourier transform computation which is highly concurrent. The architecture consists of two, o...
Sohil Shah, Preethi Venkatesan, Deepa Sundar, Muni...
132
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KONVENS
1992
15 years 8 months ago
Flexible Semantics Communication in Integrated Speech / Language Architectures
: We consider communication between modules in an integrated architecture for Speech and Natural Language (NL), in particular the communication with the semantics module. In an int...
Abdel Kader Diagne, John Nerbonne
142
Voted
VL
2005
IEEE
107views Visual Languages» more  VL 2005»
15 years 9 months ago
Navigating Software Architectures with Constant Visual Complexity
Abstract— Visualizing software architecture faces the challenges of both data complexity and visual complexity. This paper presents an approach for visualizing software architect...
Wanchun Li, Peter Eades, Seok-Hee Hong
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
15 years 8 months ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
ASPDAC
2007
ACM
135views Hardware» more  ASPDAC 2007»
15 years 8 months ago
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications
- Most image processing applications are computationally intensive and data intensive. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these a...
Yazhuo Dong, Yong Dou