3893 search results - page 209 / 779 » Execution Architectures and Compilation |
138
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ICS
2004
Tsinghua U.
15 years 9 months ago
2004
Tsinghua U.
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
137
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MICRO
2005
IEEE
15 years 9 months ago
2005
IEEE
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
149
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LCPC
2004
Springer
15 years 9 months ago
2004
Springer
Abstract. Empirical optimizers like ATLAS have been very effective in optimizing computational kernels in libraries. The best choice of parameters such as tile size and degree of l...
136
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
123
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FCCM
2006
IEEE
15 years 10 months ago
2006
IEEE
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...