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2002
IEEE
15 years 9 months ago
A Static Timing Analysis Environment Using Java Architecture for Safety Critical Real-Time Systems
Certainly, in hard real-time systems, it is reasonable to argue that no hard real-time threads should behave in an unpredictable way and that schedulability should be guaranteed b...
Erik Yu-Shing Hu, Guillem Bernat, Andy J. Wellings
FCCM
2009
IEEE
134views VLSI» more  FCCM 2009»
15 years 8 months ago
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
DATE
2004
IEEE
105views Hardware» more  DATE 2004»
15 years 7 months ago
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. Th...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
140
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PPAM
2007
Springer
15 years 10 months ago
Parallel Tiled QR Factorization for Multicore Architectures
As multicore systems continue to gain ground in the High Performance Computing world, linear algebra algorithms have to be reformulated or new algorithms have to be developed in or...
Alfredo Buttari, Julien Langou, Jakub Kurzak, Jack...
ICPADS
2006
IEEE
15 years 10 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...