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CGO
2005
IEEE
15 years 11 months ago
A Progressive Register Allocator for Irregular Architectures
Register allocation is one of the most important optimizations a compiler performs. Conventional graphcoloring based register allocators are fast and do well on regular, RISC-like...
David Koes, Seth Copen Goldstein
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 9 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
CASCON
1996
111views Education» more  CASCON 1996»
15 years 6 months ago
A hybrid process for recovering software architecture
A large portion of the software used in industry today is legacy software. Legacy systems often evolve into dicult to maintain systems whose original design has been lost or else ...
Vassilios Tzerpos, Richard C. Holt
WSC
2001
15 years 6 months ago
An agent architecture for implementing command and control in military simulations
In models of military operations it is important to include the Command and Control (C2) process in order to achieve a realistic simulation of a military force's behaviour an...
Colin R. Mason, James Moffat
DAC
2001
ACM
16 years 6 months ago
Clustered VLIW Architectures with Predicated Switching
In order to meet the high throughput requirements of applications exhibiting high ILP, VLIW ASIPs may increasingly include large numbers of functional unitsFUs. Unfortunately, `sw...
Margarida F. Jacome, Gustavo de Veciana, Satish Pi...