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ASPLOS
1998
ACM
15 years 9 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...
ISCA
1999
IEEE
96views Hardware» more  ISCA 1999»
15 years 9 months ago
PipeRench: A Coprocessor for Streaming multimedia Acceleration
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes ...
Seth Copen Goldstein, Herman Schmit, Matthew Moe, ...
OOPSLA
2010
Springer
15 years 3 months ago
Hera-JVM: a runtime system for heterogeneous multi-core architectures
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
Ross McIlroy, Joe Sventek
ENTCS
2002
166views more  ENTCS 2002»
15 years 5 months ago
Translation and Run-Time Validation of Optimized Code
The paper presents approaches to the validation of optimizing compilers. The emphasis is on aggressive and architecture-targeted optimizations which try to obtain the highest perf...
Lenore D. Zuck, Amir Pnueli, Yi Fang, Benjamin Gol...
IROS
2009
IEEE
177views Robotics» more  IROS 2009»
16 years 1 days ago
A learning approach to integration of layers of a hybrid control architecture
— Hybrid deliberative-reactive control architectures are a popular and effective approach to the control of robotic navigation applications. However, the design of said architect...
Matthew Powers, Tucker R. Balch