3893 search results - page 251 / 779 » Execution Architectures and Compilation |
195
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PPOPP
2009
ACM
16 years 6 months ago
2009
ACM
Recent advances in polyhedral compilation technology have made it feasible to automatically transform affine sequential loop nests for tiled parallel execution on multi-core proce...
167
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SASP
2008
IEEE
15 years 12 months ago
2008
IEEE
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...
165
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ICRA
2007
IEEE
15 years 11 months ago
2007
IEEE
— Recent years are seeing a renewed interest in general multi-robot architectures, capable of automating coordination. However, few architectures explore integration of multiple ...
151
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DSD
2003
IEEE
15 years 10 months ago
2003
IEEE
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
168
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ICDCSW
2003
IEEE
15 years 10 months ago
2003
IEEE
Smart Messages (SMs) are migratory execution units used to describe distributed computations over mobile ad hoc networks of embedded systems. The main benefits provided by SMs ar...