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DATE
2009
IEEE
189views Hardware» more  DATE 2009»
15 years 4 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
PPOPP
2010
ACM
15 years 4 months ago
An adaptive performance modeling tool for GPU architectures
This paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. The model is designed to provide performance information ...
Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. P...
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
15 years 2 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
ISCAPDCS
2007
14 years 11 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi
DAC
2007
ACM
15 years 10 months ago
Implicitly Parallel Programming Models for Thousand-Core Microprocessors
This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly paralle...
Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H....