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VLSID
2007
IEEE
98views VLSI» more  VLSID 2007»
15 years 10 months ago
Power Reduction in VLIW Processor with Compiler Driven Bypass Network
Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
PACT
1997
Springer
15 years 1 months ago
Estimating the Parallel Start-Up Overhead for Parallelizing Compilers
A technique for estimating the cost of executing a loop nest in parallel (parallel start-up overhead) is described in this paper. This technique is of utmost importance for paralle...
Rizos Sakellariou
ASPDAC
2007
ACM
117views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Short-Circuit Compiler Transformation: Optimizing Conditional Blocks
Abstract-- We present the short-circuit code transformation technique, intended for embedded compilers. The transformation technique optimizes conditional blocks in high-level prog...
Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau
APCSAC
2005
IEEE
15 years 3 months ago
A Stream Architecture Supporting Multiple Stream Execution Models
Multimedia devices demands a platform integrated various functional modules and an increasing support of multiple standards. Stream architecture is able to solve the problem. Howev...
Nan Wu, Mei Wen, Haiyan Li, Li Li, Chunyuan Zhang
ECMAST
1998
Springer
96views Multimedia» more  ECMAST 1998»
15 years 2 months ago
An Execution Architecture for Synchronized Multimedia Presentations
We have de ned an execution architecture for playing back synchronized multimedia documents. We suppose that such documents i ed by means of several abstractions including hypertim...
Franck Rousseau, Andrzej Duda